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PSoC(R) Mixed-Signal Array
Automotive: CY8C21323
Preliminary Data Sheet
Features
Powerful Harvard Architecture Processor M8C Processor Speeds to 12 MHz Low Power at High Speed 4.75V to 5.25V Operating Voltage Automotive Temperature Range: -40C to +125C Advanced Peripherals (PSoC Blocks) 4 Analog Type "E" PSoC Blocks Provide: - 2 Comparators with DAC Refs - Single or Dual 8-Bit 8:1 ADC 4 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Full-Duplex UART, SPITM Master or Slave - Connectable to All GPIO Pins Complex Peripherals by Combining Blocks Flexible On-Chip Memory 4K Flash Program Storage 100 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes Complete Development Tools Free Development Software (PSoCTM Designer) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128 Bytes Trace Memory Precision, Programmable Clocking Internal 4% 24 MHz Oscillator Internal Oscillator for Watchdog and Sleep Programmable Pin Configurations 25 mA Drive on All GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO Up to 8 Analog Inputs on GPIO Configurable Interrupt on All GPIO Additional System Resources I2CTM Master, Slave and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference
PSoCTM Functional Overview
The PSoC(R) family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, as well as programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The PSoC architecture, as illustrated on the left, is comprised of four main areas: the Core, the System Resources, the Digital System, and the Analog System. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each PSoC device includes four digital blocks. Depending on the PSoC package, up to two analog comparators and up to 16 general purpose IO (GPIO) are also included. The GPIO provide access to the global digital and analog interconnects.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The
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CY8C21323 Automotive Preliminary Data Sheet
PSoCTM Overview
CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two MIPS 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such as digital clocks to increase the flexibility of the PSoC mixed-signal arrays, I2C functionality for implementing an I2C master, slave, MultiMaster, an internal voltage reference that provides an absolute value of 1.3V to a number of PSoC subsystems, and various system resets supported by the M8C. The Digital System is composed of an array of digital PSoC blocks, which can be configured into any number of digital peripherals. The digital blocks can be connected to the GPIO through a series of global busses that can route any signal to any pin. Freeing designs from the constraints of a fixed peripheral controller. The Analog System is composed of four analog PSoC blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision.
Port 1 Port 0
Digital Clocks FromCore
To System Bus
To Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input Configuration
Row 0
DBB00 DBB01 DCB02 DCB03
4
Row Output Configuration
4
8 8
8 8
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below.

Digital System Block Diagram
The Analog System
The Analog System is composed of 4 configurable blocks to allow creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.
PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 4) SPI master and slave I2C slave, master, multi-master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 4) Pseudo Random Sequence Generators (8 to 32 bit)
Analog-to-digital converters (single or dual, with 8-bit resolution) Pin-to-pin comparators (1) Single-ended comparators (up to 2) with absolute (1.3V) reference or 8-bit DAC reference 1.3V reference (as a System Resource)

The digital blocks can be connected to any GPIO through a series of global busses that can route any signal to any pin. The busses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled "PSoC Device Characteristics" on page 3.
In most PSoC devices, analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. The CY8C21x23 devices provide limited functionality Type "E" analog blocks. Each column contains one CT block and one SC block. The number of blocks is on the device family which is detailed in the table titled "PSoC Device Characteristics" on page 3.
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PSoCTM Overview
PSoC Device Characteristics
Array Input Configuration
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below. PSoC Device Characteristics
Analog Columns
ACI0[1:0]
ACI1[1:0]
Analog Outputs
Analog Inputs
Analog Blocks
Digital Blocks
Digital IO
Digital Rows
SRAM Size
PSoC Part Number
ACOL1MUX
CY8C29x66 CY8C27x43 CY8C24x94
up to 64 up to 44 49 up to 24 up to 24 up to 28 16
4 2 1 1 1 1 1
16 8 4 4 4 4 4
12 12 48 12 12 28 8
4 4 2 2 2 0 0
4 4 2 2 2 2 2
12 12 6 6 6 4a 4a
2K 256 Bytes 1K 256 Bytes 256 Bytes 512 Bytes 256 Bytes
Array
ACE00 ASE10
ACE01 ASE11
CY8C24x23 CY8C24x23A CY8C21x34 CY8C21x23
Analog System Block Diagram, CY8C21323
a. Limited analog functionality.
Additional System Resources
System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource are presented below.
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs.
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Flash Size
32K 16K 16K 4K 4K 8K 4K
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PSoCTM Overview
Getting Started
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual, which can be found on http://www.cypress.com/psoc. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com.
Development Tools
PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.
Development Kits
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
PSoC TM Designer
Graphical Designer Interface
Context Sensitive Help
Commands
Results
Technical Training
Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details.
Importable Design Database Device Database Application Database Project Database User Modules Library
Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants.
PSoC TM Designer Core Engine
PSoC Configuration Sheet
Manufacturing Information File
Technical Support
PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.
Em ulation Pod In-Circuit Em ulator Device Programmer
Application Notes
A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are sorted by date by default.
PSoC Designer Subsystems
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PSoCTM Overview
PSoC Designer Software Subsystems
Device Editor
The device editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework.
Debugger
The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the parallel or USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (12 MHz) operation
Design Browser
The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.
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CY8C21323 Automotive Preliminary Data Sheet
PSoCTM Overview
Designing with User Modules
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, busses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.
Device Editor
User Module Selection Placement and Parameter -ization Source Code Generator
Generate Application
Application Editor
Project Manager Source Code Editor Build Manager
Build All
Debugger
Interface to ICE Storage Inspector Event & Breakpoint Manager
User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
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PSoCTM Overview
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym AC ADC API CPU CT DAC DC EEPROM FSR GPIO IO IPOR LSb LVD MSb PC POR PPOR PSoCTM PWM ROM SC SRAM alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose IO input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter power on reset precision power on reset Programmable System-on-Chip pulse width modulator read only memory switched capacitor static random access memory Description
Table of Contents
For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Reference Manual on http://www.cypress.com. This data sheet encompasses and is organized into the following chapters and sections.
1. Pin Information ............................................................. 8 1.1 Pinouts ................................................................... 8 1.1.1 20-Pin Part Pinout .................................... 8 Register Reference ....................................................... 9 2.1 Register Conventions ............................................. 9 2.2 Register Mapping Tables ....................................... 9 Electrical Specifications ............................................ 12 3.1 Absolute Maximum Ratings ................................ 13 3.2 Operating Temperature ....................................... 13 3.3 DC Electrical Characteristics ................................ 13 3.3.1 DC Chip-Level Specifications ................... 13 3.3.2 DC General Purpose IO Specifications .... 14 3.3.3 DC Amplifier Specifications ..................... 14 3.3.4 DC POR and LVD Specifications ............. 15 3.3.5 DC Programming Specifications ............... 15 3.4 AC Electrical Characteristics ................................ 16 3.4.1 AC Chip-Level Specifications ................... 16 3.4.2 AC General Purpose IO Specifications .... 17 3.4.3 AC Amplifier Specifications ...................... 18 3.4.4 AC Digital Block Specifications ................. 18 3.4.5 AC External Clock Specifications ............. 19 3.4.6 AC Programming Specifications ............... 19 3.4.7 AC I2C Specifications ............................... 20 Packaging Information ............................................... 21 4.1 Packaging Dimensions ......................................... 21 4.2 Thermal Impedances .......................................... 22 4.3 Solder Reflow Peak Temperature ........................ 22 Ordering Information .................................................. 23 5.1 Ordering Code Definitions ................................... 23 Sales and Service Information .................................. 24 6.1 Revision History .................................................. 24 6.2 Copyrights and Flash Code Protection ................ 24
2.
3.
4.
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 14 lists all the abbreviations used to measure the PSoC devices.
5. 6.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal.
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1. Pin Information
This chapter describes, lists, and illustrates the CY8C21323 PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C21323 PSoC device is available in one package, which is listed and illustrated in the following table. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
1.1.1
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO IO IO IO IO IO IO IO IO IO IO IO
20-Pin Part Pinout
Type
Table 1-1. 20-Pin Part Pinout (SSOP)
Digital IO IO IO IO Power Analog I I I I Name P0[7] P0[5] P0[3] P0[1] Vss P1[7] P1[5] P1[3] P1[1] Power Vss P1[0] P1[2] P1[4] P1[6] Input I I I I Power XRES P0[0] P0[2] P0[4] P0[6] Vdd Active high external reset with internal pull down. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. Optional External Clock Input (EXTCLK). I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. I2C Serial Data (SDA), ISSP-SDATA*. Description Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Ground connection. I2C Serial Clock (SCL). I2C Serial Data (SDA).
CY8C21323 20-Pin PSoC Device
A, I, P0[7] A, I, P0[5] A, I, P0[3] A, I, P0[1] Vss I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, P1[1] Vss
1 2 3 4 5 6 7 8 9 10
SSOP
20 19 18 17 16 15 14 13 12 11
Vdd P0[6], A, I P0[4], A, I P0[2], A, I P0[0], A, I XRES P1[6] P1[4],EXTCLK P1[2] P1[0],I2C SDA
LEGEND A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
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2. Register Reference
This chapter lists the registers of the CY8C21323 PSoC device. For detailed register information, reference the PSoC Mixed-Signal Array Technical Reference Manual.
2.1
Register Conventions
2.2
Register Mapping Tables
The register conventions specific to this section are listed in the following table.
Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are Reserved and should not be accessed.
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2. Register Reference
Register Map Bank 0 Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 48 09 49 0A 4A 0B 4B 0C 4C 0D 4D 0E 4E 0F 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00DR0 20 # AMX_IN 60 DBB00DR1 21 W 61 DBB00DR2 22 RW PWM_CR 62 DBB00CR0 23 # 63 DBB01DR0 24 # CMP_CR0 64 DBB01DR1 25 W 65 DBB01DR2 26 RW CMP_CR1 66 DBB01CR0 27 # 67 DCB02DR0 28 # ADC0_CR 68 DCB02DR1 29 W ADC1_CR 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # TMP_DR0 6C DCB03DR1 2D W TMP_DR1 6D DCB03DR2 2E RW TMP_DR2 6E DCB03CR0 2F # TMP_DR3 6F 30 70 31 71 32 ACE00CR1 72 33 ACE00CR2 73 34 74 35 75 36 ACE01CR1 76 37 ACE01CR2 77 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed.
PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2
RW RW # RW # #
RW RW RW RW
RW RW
RW RW
80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific.
ASE10CR0
RW
RW
I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT
DEC_CR0 DEC_CR1
RW RW RW RW RW RW RW CPU_F
CPU_SCR1 CPU_SCR0
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
RW # RW # RW RW RW RW RW RW RC W
RW RW
RL
# #
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2. Register Reference
Register Map Bank 1 Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
00 RW 40 01 RW 41 02 RW 42 03 RW 43 04 RW 44 05 RW 45 06 RW 46 07 RW 47 08 48 09 49 0A 4A 0B 4B 0C 4C 0D 4D 0E 4E 0F 4F 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 1A 5A 1B 5B 1C 5C 1D 5D 1E 5E 1F 5F DBB00FN 20 RW CLK_CR0 60 DBB00IN 21 RW CLK_CR1 61 DBB00OU 22 RW ABF_CR0 62 23 AMD_CR0 63 DBB01FN 24 RW CMP_GO_EN 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 27 ALT_CR0 67 DCB02FN 28 RW 68 DCB02IN 29 RW 69 DCB02OU 2A RW 6A 2B CLK_CR3 6B DCB03FN 2C RW TMP_DR0 6C DCB03IN 2D RW TMP_DR1 6D DCB03OU 2E RW TMP_DR2 6E 2F TMP_DR3 6F 30 70 31 71 32 ACE00CR1 72 33 ACE00CR2 73 34 74 35 75 36 ACE01CR1 76 37 ACE01CR2 77 38 78 39 79 3A 7A 3B 7B 3C 7C 3D 7D 3E 7E 3F 7F Blank fields are Reserved and should not be accessed.
PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1
ASE10CR0
RW RW RW RW RW RW RW
RW RW RW RW RW
RW RW
RW RW
80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific.
RW
RW
RW RW RW RW RW RW RW
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 D8 D9 DA DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 ADC0_TR E5 ADC1_TR E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FLS_PR1 FA FB FC FD CPU_SCR1 FE CPU_SCR0 FF
RW RW RW RW
RW RW RW RW RW RW RW R RW RW W W RW W
RL
RW
# #
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3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C21x23 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 125oC and TJ 135oC, except where noted.
5.25
O
lid n g Va r ati n pe g io Re
4.75 Vdd Voltage 3.00 2.40 93 kHz 3 MHz
12 MHz CPU Fre que ncy
24 MHz
Figure 3-1a. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol
oC
Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
Symbol
W
Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
dB fF Hz KB Kbit kHz k MHz M
A F H s V Vrms
mA ms mV nA ns nV
pA pF pp ppm ps sps
V
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CY8C21323 Automotive Preliminary Data Sheet
3. Electrical Specifications
3.1
Symbol TSTG
Absolute Maximum Ratings
Description Storage Temperature Min -55 Typ +25 Max +125 Units
oC
Table 3-2. Absolute Maximum Ratings
Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25C +/- 25C. Storage temperatures above 65oC will degrade reliability. Maximum combined storage and operational time at +125C is 7000 hours.
TA Vdd VIO VIOZ IMIO ESD LU
Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current
-40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 -
- - - - - - -
+125 +6.0
o
C
V
Vdd + 0.5 V Vdd + 0.5 V +25 - 200 mA V mA Human Body Model ESD.
3.2
Symbol TA TJ
Operating Temperature
Description Ambient Temperature Junction Temperature Min -40 -40 - - Typ Max +125 +135 Units
oC o
Table 3-3. Operating Temperature
Notes The temperature rise from ambient to junction is package specific. See "Thermal Impedances per Package" on page 22. The user must limit the power consumption to comply with this requirement.
C
3.3
3.3.1
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-4. DC Chip-Level Specifications
Symbol Vdd IDD Supply Voltage Supply Current, IMO = 24 MHz Description Min 4.75 - - 3 Typ Max 5.25 4 V mA Units Notes See DC POR and LVD specifications, Table 3-7 on page 15. Conditions are Vdd = 5.0V, 25oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Vdd = 5.25V, -40oC TA 55oC. Vdd = 5.25V, 55oC TA 125oC. Trimmed for appropriate Vdd. Vdd = 4.75V to 5.25V.
ISB ISBH VREF AGND
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference Voltage (Bandgap) Analog Ground
- - 1.28 VREF - 0.003
5 5 1.30 VREF
12 100 1.32 VREF + 0.003
A A
V V
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CY8C21323 Automotive Preliminary Data Sheet
3. Electrical Specifications
3.3.2
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-5. DC GPIO Specifications
Symbol RPU RPD VOH Pull-up Resistor Pull-down Resistor High Output Level Description 4 4 3.5 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. Vdd = 4.75 to 5.25. Vdd = 4.75 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes
VOL
Low Output Level
-
-
0.75
V
VIL VIH VH IIL CIN COUT
Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.1 - - - -
- - 60 1 3.5 3.5
0.8
V V
- - 10 10
mV nA pF pF
3.3.3
DC Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-6. DC Amplifier Specifications
Symbol VOSOA TCVOSOA IEBOA CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current - - - - 0.0 - - Min 10 200 4.5 - 80 10 Typ 2.5 15 - - 9.5 Vdd - 1 - 100 Max Units mV
V/oC
Notes
pA pF V dB
A
Gross tested to 1 A. Package and pin dependent. Temp = 25oC.
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CY8C21323 Automotive Preliminary Data Sheet
3. Electrical Specifications
3.3.4
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-7. DC POR and LVD Specifications
Symbol VPPOR2 PORLEV[1:0] = 10b Vdd Value for LVD Trip VLVD6 VLVD7 VM[2:0] = 110b VM[2:0] = 111b 4.62 4.71 4.73 4.81 4.83 4.95 V V Description Vdd Value for PPOR Trip 4.55 4.70 V Min Typ Max Units Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.
3.3.5
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-8. DC Programming Specifications
Symbol VddIWRITE IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Voltage for Flash Write Operations Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total) Flash Data Retentionc
a, b a
Min 4.75 - - 2.2 - - - 3.5 100 6400 15
0
Typ - 5 - - - - - - - - -
0
Max - 25 0.8 - 0.2 1.5 V
Units mA V V mA mA
Notes
Driving internal pull-down resistor. Driving internal pull-down resistor.
Vss + 0.75 V Vdd - - -
0
V - -
0
Erase/write cycles per block. Erase/write cycles.0
Years
a. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information b. A maximum of 36 x 100 block endurance cycles is allowed. c. Flash data retention based on the use condition of 7000 hours at TA 125C and the remaining time at TA 65C.
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CY8C21323 Automotive Preliminary Data Sheet
3. Electrical Specifications
3.4
3.4.1
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only..
Table 3-9. AC Chip-Level Specifications
Symbol FIMO24 FCPU1 FBLK5 F32K1 Jitter32k Jitter32k TXRST DC24M Step24M Jitter24M1 FMAX TRAMP Description Internal Main Oscillator Frequency for 24 MHz CPU Frequency (5V Nominal) Digital PSoC Block Frequency0(5V Nominal) Internal Low Speed Oscillator Frequency 32 kHz RMS Period Jitter 32 kHz Peak-to-Peak Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 24 MHz Peak-to-Peak Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time Min 23.4 0.09 0 15 - - 10 40 - - - 0 24 12 24 32 100 250 - 50 50 600 - - 12.48 - Typ Max 24.6 12.48 24.96 64 600 - - 60 - Units MHz MHz MHz kHz ns ns
s
Notes
Refer to the AC Digital Block Specifications below.
% kHz ps MHz
s
Jitter24M1
F24M
Figure 3-2. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K1
Figure 3-3. 32 kHz Period Jitter (ILO) Timing Diagram
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CY8C21323 Automotive Preliminary Data Sheet
3. Electrical Specifications
3.4.2
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-10. AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO TRiseF TFallF TRiseS TFallS
GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF
0 2 2 7 7
- - - 27 22
12.48 22 22 - -
MHz ns ns ns ns
Normal Strong Mode Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90%
90%
GPIO Pin
10%
TRiseF TRiseS
TFallF TFallS
Figure 3-4. GPIO Timing Diagram
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CY8C21323 Automotive Preliminary Data Sheet
3. Electrical Specifications
3.4.3
AC Amplifier Specifications
The following table list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 3-11. AC Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TCOMP1
Comparator Mode Response Time, 50 mVpp Signal Centered on Ref
150
ns
3.4.4
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-12. AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All Functions Timer
Maximum Block Clocking Frequency (> 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With or Without Capture 50a - - 50 - - 20 50 50 - - - - - 50 - - - - - - - - - - - - - - - - - - -
24.96 - 24.96 24.96 - 24.96 24.96 - - - 24.96 24.96 24.96 4.1 2.05 - 8.2 24.96
MHz ns MHz MHz ns MHz MHz ns ns ns MHz MHz MHz MHz MHz ns MHz MHz
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Counter
Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input
4.75V < Vdd < 5.25V.
Dead Band
Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency
4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency
Maximum data rate at 4.1 MHz due to 2 x over clocking.
Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
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CY8C21323 Automotive Preliminary Data Sheet
3. Electrical Specifications
3.4.5
AC External Clock Specifications
The following table list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-13. AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT - - -
Frequency High Period Low Period Power Up IMO to Switch
0.093 20.6 20.6 150
- - - -
24.24 5300 - -
MHz ns ns
s
3.4.6
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-14. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK
Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK
1 1 40 40 0 - - -
- - - - - 15 30 -
20 20 - - 8 - - 50
ns ns ns ns MHz ms ms ns
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CY8C21323 Automotive Preliminary Data Sheet
3. Electrical Specifications
3.4.7
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 125C. Typical parameters apply to 5V at 25C and are for design guidance only.
Table 3-15. AC Characteristics of the I2C SDA and SCL Pins for Vcc 4.75V
Standard Mode Symbol Description Min Max Fast Mode Min Max Units Notes
FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C
SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time0 Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter.
0 4.0 4.7 4.0 4.7 0 2500 4.0 4.7 -
100 - - - - - -0 - - -
0 0.6 1.3 0.6 0.6 0 100a 0.6 1.3 0
400 - - - - - -0 - - 50
kHz
s s s s s
ns0
s s
ns
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL
Figure 3-5. Definition for Timing for Fast/Standard Mode on T I2C Bus the
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4. Packaging Information 4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C21323 PSoC device, along with the thermal impedances for each package and minimum solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim.
4.1
Packaging Dimensions
51-85077 *C
Figure 4-1. 20-Lead (210-MIL) SSOP
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CY8C21323 Automotive Preliminary Data Sheet
4. Packaging Information
4.2
Thermal Impedances
Typical JA *
Table 4-1. Thermal Impedances per Package
Package
20 SSOP * TJ = TA + POWER x JA
117 oC/W
4.3
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 4-2. Solder Reflow Peak Temperature
Package Minimum Peak Temperature* Maximum Peak Temperature
20 SSOP
240oC
260oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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5. Ordering Information
The following table lists the CY8C21323 PSoC device's key package features and ordering codes.
PSoC Device Key Features and Ordering Information
Switch Mode Pump Digital PSoC Blocks Temperature Range XRES Pin Yes Yes Digital IO Pins Ordering Code Package Analog Outputs 0 0 Flash (Bytes) RAM (Bytes) Analog Blocks Analog Inputs 8 8
20 Pin (210-Mil) SSOP 20 Pin (210-Mil) SSOP (Tape and Reel)
CY8C21323-12PVXE CY8C21323-12PVXET
4K 4K
256 256
No No
-40C to +125C -40C to +125C
4 4
4 4
16 16
5.1
Ordering Code Definitions
CY 8 C 21 xxx-12xx
Package Type: PX = PDIP Pb-Free SX = SOIC Pb-Free PVX = SSOP Pb-Free LFX = QFN Pb-Free AX = TQFP Pb-Free Speed: 12 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended
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6. Sales and Service Information
Cypress Semiconductor 198 Champion Court San Jose, CA 95134 408.943.2600
Web Sites:
Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm
6.1
Revision History
Document Title: CY8C21323 Automotive PSoC Mixed-Signal Array Preliminary Data Sheet Document Number: 001-06161 Revision ECN # Issue Date Origin of Change Description of Change ** 414127 See ECN HMT New silicon and document (Revision **). Posting: None Distribution: External/Public
6.2
Copyrights
Copyrights and Flash Code Protection
(c) Cypress Semiconductor Corp. 2005. All rights reserved. PSoC(R) is a registered trademark and PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor.
Flash Code Protection
Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its PSoC family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products.
January 16, 2006
(c) Cypress Semiconductor Corp. 2005 -- Document No. 001-06161 Rev. **
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